Formalisation and Validation of the Std Logic 1164 and Numeric Std VHDL Packages using the NqthmTheorem

When synthesizing complex digital circuits, it is extremely important to have high conndence in the library of components and functions. This paper deals with the validation of two standardized VHDL packages that were developed for circuit synthesis and which, at the same time, are compatible with enhanced multi-valued simulation tools. The Boyer-Moore theorem prover has been used for this purpose. The paper introduces an eecient and general strategy for utilizing the basic concepts of the Boyer-Moore system to prove the theorems that establish the mathematical properties of the package functions.